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CY15B256J 256-kbit (32k 8) automotive serial (i 2 c) f-ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-90843 rev. *i revised february 28, 2018 256-kbit (32k 8) automotive serial (i 2 c) f-ram features 256-kbit ferroelectric random access memory (f-ram) logically organized as 32k 8 ? high-endurance 100 trillion (10 14 ) read/writes ? 151-year data retention (see data retention and endurance on page 13 ) ? nodelay? writes ? advanced high-reliability ferroelectric process fast two-wire serial interface (i 2 c) ? up to 3.4-mhz frequency [1] ? direct hardware replacement for serial eeprom ? supports legacy timings for 100 khz and 400 khz device id ? manufacturer id and product id low-power consumption ? 175 ? a active current at 100 khz ? 150 ? a standby current ? 8 ? a sleep mode current low-voltage operation: v dd = 2.0 v to 3.6 v automotive-a temperature: C40 ? c to +85 ? c 8-pin small outline integrated circuit (soic) package restriction of hazardous su bstances (rohs) compliant functional description the CY15B256J is a 256-kbit nonvolatile memory employing an advanced ferroelectric process. an f-ram is nonvolatile and performs reads and writes similar to a ram. it provides reliabl e data retention for 151 years while eliminating the complexities , overhead, and system-level re liability problems caused by eeprom and other nonvo latile memories. unlike eeprom, the CY15B256J performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately af ter each byte is successfully transferred to the device. the next bus cycle can commence without the need for data polling. in addition, the product off ers substantial write endurance compared with ot her nonvolatile memories. f-ram also exhibits much lower power during writes than eeprom because write operations do not require an internally elevated power supply voltage for write circuits. th e CY15B256J is capable of supporting 10 14 read/write cycles, or 100 million times more w rite cycles than eeprom. these capabilities make the CY15B256J ideal for nonvolatile memory applications, requirin g frequent or rapid writes. examples range from data logg ing, where the number of write cycles may be critical, to demandi ng industrial controls where the long write time of eeprom can cause data loss. the combination of features allows more frequent data writing with less overhead for the system. the CY15B256J provides substantial benefits to users of serial eeprom as a hardware drop-in replacement. the device incorporates a read-only device id that allows the host to determine the manufacturer, product density, and product revision. the device specific ations are guaranteed over an automotive-a temperature range of C40 ? c to +85 ? c. for a complete list of re lated documentation, click here . logic block diagram address latch 32 k x 8 f-ram array data latch 8 sda counter serial to parallel converter control logic scl wp a0-a2 device id and manufacturer id 8 15 8 note 1. the CY15B256J does not meet the nxp i 2 c specification in the fast-mode plus (fm+, 1 mhz) for i ol and in the high speed mode (hs-mode, 3.4 mhz) for v hys . refer to dc electrical characteristics on page 12 for more details.
CY15B256J document number: 001-90843 rev. *i page 2 of 21 contents pinout ........................................................ ........................ 3 pin definitions ............................................... ................... 3 functional overview ........................................... ............. 4 memory architecture ........................................... ............. 4 two-wire interface ............ ........... ........... .......... ................ 4 stop condition (p) ............................................ ......... 5 start condition (s) ........................................... ........ 5 data/address transfer ......................................... ....... 5 acknowledge/no-acknowledge . .................................. 6 high-speed mode (hs-mode) ..................................... 6 slave device address ....... ................................... ....... 7 addressing overview ........ ................................... ....... 7 data transfer ................................................. ............. 7 memory operation .............................................. .............. 8 write operation ............................................... ............ 8 read operation ................................................ ........... 9 sleep mode .................................................... ........... 10 device id ..................................................... .................... 11 maximum ratings ............................................... ............ 12 operating range ............................................... .............. 12 dc electrical characteristics ................................. ....... 12 data retention and endurance .................................. ... 13 capacitance ................................................... ................. 13 thermal resistance ............................................ ............ 13 ac test loads and waveforms ................................... .. 13 ac test conditions ............................................ ............ 13 ac switching characteristics .................................. ..... 14 power cycle timing ............................................ ........... 15 ordering information .......................................... ............ 16 ordering code definitions ..................................... .... 16 package diagram ............................................... ............. 17 acronyms ...................................................... .................. 18 document conventions .......................................... ....... 18 units of measure .............................................. ......... 18 document history page ......................................... ........ 19 sales, solutions, and legal information ...................... 2 1 worldwide sales and design s upport ......... .............. 21 products ...................................................... .............. 21 psoc? solutions ............................................... ....... 21 cypress developer community . ................................ 21 technical support ........... .................................. ........ 21
CY15B256J document number: 001-90843 rev. *i page 3 of 21 pinout figure 1. 8-pin soic pinout wp scl 1 2 3 4 5 a0 8 7 6 v dd sda a1 top view not to scale v ss a2 3lhillwlrv 3l1dph ,27sh hvfulswlr a0Ca2 input device select address 0C2 . these pins are used to select one of up to eight devices of t he same type on the same two-wire bus. to select the device, the address val ue on the three pins must match the corresponding bits contained in the slave addre ss. the address pins are pulled down internally. sda input/output serial data address . this is a bidirectional pin for the two-wire interface. it is open-drain and is intended to be wire-and'd with other devices on the two-wire bu s. the input buffer incorporates a schmitt trigger for noise immun ity and the output driver includ es slope control for falling edges. an external pull-up resistor is required. scl input serial clock . the serial clock pin for the t wo-wire interface. data is cloc ked out of the part on the falling edge, and into the device on the rising edge. the scl input als o incorporates a schmitt trigger input for noise immunity. wp input write protect . when tied to v dd , addresses in the entire memory map will be write-protected. w hen wp is connected to ground, all addresses are write enabled. thi s pin is pulled down internally. v ss power supply ground for the device. must be c onnected to the gro und of the system. v dd power supply power suppl y input to the device.
CY15B256J document number: 001-90843 rev. *i page 4 of 21 functional overview the CY15B256J is a serial f-ram memory. the memory array is logically organized as 32,768 8 bits and is accessed using a two-wire (i 2 c) interface. the functional operation of the f-ram is similar to serial eeprom. t he major difference between the CY15B256J and a serial eeprom with the same pinout is the f-ram's superior write performance, high endurance, and low power consumption. memory architecture when accessing the CY15B256J, the user addresses 32k locations of eight data bits each. these eight data bits are sh ifted in or out serially. the addresses are accessed using the two-wi re protocol, which includes a slave address (to distinguish other non-memory devices) and a two-byte address. the upper msb bit of the address range is 'don't care' value. the complete address of 15 bits specifies each byte address uniquely. the access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the two-wire bus. unl ike a serial eeprom, it is not nece ssary to poll the device for a ready condition because writes occur at bus speed. by the time a new bus transaction can be shifted into the device, a write operation is complete. this is explained in more detail in memory operation on page 8 . two-wire interface the CY15B256J employs a bidirectional two-wire bus protocol using few pins or board space. figure 2 illustrates a typical system configuration usin g the CY15B256J in a microcontroller-based system. the two-wire bus is familiar to many users but is described in this section. by convention, any device that is sending data to the bus is th e transmitter while the target device for this data is the receiv er. the device that is controlling the bus is the master. the maste r is responsible for generating the clock signal for all operatio ns. any device on the bus that is be ing controlled is a slave. the CY15B256J is always a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions including start, stop, data bit, or acknowledge. figure 3 on page 5 and figure 4 on page 5 illustrate the signal conditions that specify the four states. detailed timing diagrams are shown in the electrical specifications section. the CY15B256J does not meet the nxp i 2 c specification in the fast-mode plus (fm+, 1 mhz) for i ol and in the high speed mode (hs-mode, 3.4 mhz) for v hys . refer to dc electrical characteristics on page 12 for more details. figure 2. system configuration using serial (i 2 c) f-ram sda scl dd a0 a0 a0 a1 a1 a1 scl scl scl sda sda sda wp wp wp #0 #1 #7 a2 a2 a2 microcontroller v dd v dd v CY15B256J CY15B256J CY15B256J r pmin = (v dd - v ol max) / i ol r pmax = t r / (0.8473 * c b )
CY15B256J document number: 001-90843 rev. *i page 5 of 21 stop condition (p) a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations using the CY15B256J should en d with a stop condition. if an operation is in progress when a stop is asserted, the operation will be aborted. the master must have control of the sda (not a memory read) to assert a stop condition. start condition (s) a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all commands should be preceded by a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will read y the CY15B256J for a new operation. if the power supply drops below the specified v dd minimum during operation, the system should issue a start condition prior to performi ng another operation. data/address transfer all data transfers (including addresses) take place while the s cl signal is high. except under the three conditions described above, the sda signal should n ot change while scl is high. figure 3. start and stop conditions full pagewidth sda scl p stop condition sda scl s start condition )ljuhdwd7udvihurwkh, v handbook, full pagewidth s or p sda s p scl stop or start condition s start condition 2 3 4 - 8 9 ack 9 ack 78 12 msb acknowledgement signal from slave byte complete acknowledgement signal from receiver 1
CY15B256J document number: 001-90843 rev. *i page 6 of 21 acknowledge/no-acknowledge the acknowledge takes place after the 8th data bit has been transferred in any transaction. du ring this state the transmitt er should release the sda bus to allow the receiver to drive it. t he receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condition is a no-acknowledge and the operation is aborted. the receiver will fail to acknowledge for two distinct reasons, the first being that a byte trans fer fails. in this case, the no-acknowledge ceases the current operation so that the part can be addressed again. this allows the last byte to be recovered in the event of a communication error. the second and most common reason is that, the receiver does not acknowledge to deliberately end an operation. for example, during a read operation, the CY15B256J will continue to place data on the bus as long as the receiver sends acknowledges (and clocks). when a read oper ation is complete and no more data is needed, the receiver must not acknowledge the last byte . if the receiver acknowledges the last byte, this causes the CY15B256J to attempt to drive the bus on the next clock while the master is sending a new command such as stop. high-speed mode (hs-mode) the CY15B256J supports a 3.4-mhz high-speed mode. a master code (00001xxxb) must be issued to place the device into the high-speed mode. communication between master and slave will then be enabled for speeds up to 3.4 mhz. a stop condition will exit hs-mode. single- and multiple-byte reads an d writes are supported. figure 5. acknowledge on the i 2 c bus handbook, full pagewidth s start condition 9 8 2 1 clock pulse for acknowledgement no acknowledge acknowledge data output by master data output by slave scl from master )ljuhdwd7udvihu)rupdwlv0rh handbook, full pagewidth f/s-mode hs-mode f/s-mode 01 / a 1 data n (bytes + ack.) w / r s master code s slave add. hs-mode continues s slave add. p no acknowledge acknowledge or no acknowledge
CY15B256J document number: 001-90843 rev. *i page 7 of 21 slave device address the first byte that the CY15B256J expects after a start condition is the slave address. as shown in figure 7 , the slave address contains the device type or slave id, the device select address bits, and a bit that specifies if the transaction is a read or a write. bits 7C4 are the device type (slave id) and should be set to 1010b for the CY15B256J. these bits allow other function types to reside on the two-wire bus wi thin an identical address range . bits 3C1 are the device select address bits. they must match th e corresponding value on the external address pins to select the device. up to eight CY15B256J devices can reside on the same two-wire bus by assigning a different address to each. bit 0 is the read/write bit (r/w ). r/w = 1 indicates a read operation and r/w = 0 indicates a write operation. addressing overview after the CY15B256J (as receiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. the address requires two bytes. the complete 15-bit address is latched internally. each access causes the latched address value to be incremented automatically. the current address is the value that is held in the latch; either a newly written value or the address following th e last access. the current address will be held for as long as po wer remains or until a new value is written. reads always use the current address. a random read address can be loaded by beginning a write operation as explained below. after transmission of each data byte, just prior to the acknowledge, the CY15B256J increments the internal address latch. this allows the next sequential byte to be accessed with no additional addressing. after the last address (7fffh) is reached, the address latch will roll over to 0000h. there is no limit to the number of bytes that can be accessed with a single read or write operation. data transfer after the address bytes have been transmitted, data transfer between the bus master and the CY15B256J can begin. for a read operation the CY15B256J will place 8 data bits on the bus then wait for an acknowledge from the master. if the acknowledge occurs, the cy15b 256j will transfer the next sequential byte. if the acknowledg e is not sent, the CY15B256J will end the read operation. for a write operation, the CY15B256J will accept 8 data bits from the master then sends an acknowledge. all data transfer occurs msb (most significant bit) first. figure 7. memory slave device address handbook, halfpage r/w lsb msb slave id 10 1 0 a2 a0 a1 device select
CY15B256J document number: 001-90843 rev. *i page 8 of 21 memory operation the CY15B256J is designed to operate in a manner very similar to other two-wire interface memory products. the major differences result from the hi gher performance write capability of f-ram technology. these improvements result in some differences between the CY15B256J and a similar configuration eeprom during writes. the comp lete operation for both writes and reads is explained below. write operation all writes begin with a slave address, then a memory address. the bus master indicates a write operation by setting the lsb o f the slave address (r/w bit) to a '0'. after addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. any number of sequential bytes may be written. if the end of the address range is reache d internally, the address counter will wrap from 7fffh to 0000h. unlike other nonvolatile memory technologies, there is no effective write delay with f-ram. since the read and write access times of the underlying memory are the same, the user experiences no delay through th e bus. the entire memory cycle occurs in less time than a single bus clock. therefore, any operation including read or write can occur immediately followi ng a write. acknowledge polling, a technique used with eeproms to determine if a write is complete is unnecessary and will alw ays return a ready condition. internally, an actual memory write occurs after the 8th data bi t is transferred. it will be complete before the acknowledge is sent . therefore, if the user desires to abort a write without alterin g the memory contents, this should be done using start or stop condition prior to the 8th data bit. the CY15B256J uses no page buffering. the memory array can be write -protected using the wp pin. setting the wp pin to a high condition (v dd ) will write-protect all addresses. the CY15B256J will not acknowledge data bytes that are written to p rotected addresses. in addition, the addre ss counter will not increment if wr ites are attempted to these addresses. setting wp to a low state (v ss ) will disable the write protect. wp is pulled down internally. figure 8 and figure 9 below illustrate a single-byte and multiple-byte write cycles i n fast-mode plus (fm+). figure 10 below illustrate a single-by te write cycles in hs mode. figure 8. single-byte write s a slave address 0 address msb a data byte a p by master by f-ram start address & data stop acknowledge address lsb a figure 9. multi-byte write s a slave address 0 address msb a data byte a p by master by f-ram start address & data stop acknowledge address lsb a data byte a figure 10. hs-mode byte write s a slave address 0 data byte a p by master by f-ram start & enter hs-mode address & data stop & exit hs-mode s 1 start acknowledge x x x 1 0 0 0 0 hs-mode command address msb a address lsb a no acknowledge
CY15B256J document number: 001-90843 rev. *i page 9 of 21 read operation there are two basic types of read operations. they are current address read and selective address read. in a current address read, the CY15B256J uses the internal address latch to supply the address. in a selective read, the user performs a procedure to set the address to a specific value. current address & sequential read as mentioned above the CY15B256J uses an internal latch to supply the address for a read operation. a current address read uses the existing value in the address latch as a starting plac e for the read operation. the system reads from the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to a '1'. this indicates that a read operation is requested. after receiving the complete slave address, the CY15B256J will begin shifting out data from the current address on the next clock. the current address is the value held in the inte rnal address latch. beginning with the current address, the bus master can read any number of bytes. thus, a sequential read is simply a current address read with multiple byte transfers. after each byte the internal address counte r will be incremented. note each time the bus master acknowledges a byte, this indicates that the CY15B256J should read out the next sequential byte. there are four ways to properly terminate a read operation. failing to properly terminate the read will most likely create a bus contention as the CY15B256J attempts to read out additional data onto the bus. the f our valid methods are: 1. the bus master issues a no-acknowledge in the 9th clock cycle and a stop in the 10th clo ck cycle. this is illustrated i n the diagrams below. this is preferred. 2. the bus master issues a no-acknowledge in the 9th clock cycle and a star t in the 10th. 3. the bus master issues a s top in the 9th clock cycle. 4. the bus master issues a sta rt in the 9th clock cycle. if the internal address reaches 7fffh, it will wrap around to 0000h on the ne xt read cycle. figure 11 and figure 12 below show the proper operation for current address reads. figure 11. current address read s a slave address 1 data byte 1 p by master by f-ram start address stop acknowledge no acknowledge data figure 12. sequential read s a slave address 1 data byte 1 p by master by f-ram start address stop acknowledge no acknowledge data data byte a acknowledge figure 13. hs-mode current address read s a slave address 1 data byte 1 p by master by f-ram start & enter hs-mode address stop & exit hs-mode no acknowledge data s 1 start acknowledge x x x 1 0 0 0 0 hs-mode command no acknowledge
CY15B256J document number: 001-90843 rev. *i page 10 of 21 selective (random) read there is a simple technique that allows a user to select a rand om address location as the starting point for a read operation. th is involves using the first three b ytes of a write operation to se t the internal address followed by s ubsequent read operations. to perform a selective read, the bus master sends out the slave address with the lsb (r/w ) set to 0. this specifies a write operation. according to the writ e protocol, the bus master then sends the address bytes that are loaded into the internal addre ss latch. after the CY15B256J acknowledges the address, the bus master issues a start condition. this simultaneously aborts the write operation and allows the read command to be issued with the slave address lsb set to a 1. the operation is now a current address read. sleep mode a low-power mode called sleep mode is implemented on the CY15B256J device. the device will enter this low power state when the sleep command 86h is clocked-in. sleep mode entry can be entered as follows: 1. the master sends a start command. 2. the master sends reserved slave id 0xf8. 3. the CY15B256J sends an ack. 4. the master sends the i 2 c-bus slave address of the slave device it needs to identify. the last bit is a dont care val ue (r/w bit). only one device must acknowledge this byte (the one that has the i 2 c-bus slave address). 5. the CY15B256J sends an ack. 6. the master sends a re-start command. 7. the master sends res erved slave id 0x86. 8. the CY15B256J sends an ack. 9. the master sends stop to ens ure the device enters sleep mode. once in sleep mode, the device draws i zz current, but the device continues to monitor the i 2 c pins. once the master sends a slave address that the CY15B256J identifies, it will wakeup and be ready for normal operation within t rec (400 ? s max.). as an alternative method of determining when the device is ready, the master can send read or write commands and look for an ack. while the device is waking up, it will nack the master unt il it is ready. figure 14. select ive (random) read s a slave address 1 data byte 1 p by master by f-ram start address stop no acknowledge data s a slave address 0 address msb a start address acknowledge address lsb a figure 15. sleep mode entry s a p by master by f-ram start address stop s a rsvd slave id (f8) slave address a start address acknowledge rsvd slave id (86) x
CY15B256J document number: 001-90843 rev. *i page 11 of 21 device id the CY15B256J device incorporates a means of identifying the de vice by providing three bytes of data, which are manufacturer, product id, and die revision. th e device id is read-only. it ca n be accessed as follows: 1. the master sends a start command. 2. the master sends reserved slave id 0xf8 3. the CY15B256J sends an ack. 4. the master sends the i 2 c-bus slave address of the slave device it needs to iden tify. the last bit is a 'don't care' val ue (r/w bit). only one device must acknowledge this byte (the one that has the i 2 c-bus slave address). 5. the CY15B256J sends an ack. 6. the master sends a re-start command. 7. the master sends res erved slave id 0xf9. 8. the CY15B256J sends an ack. 9. the device id read can be done, starting with the 12 manufacturer bits, followed by t he 9 part identification bits, and then the 3 die revision bits. 10.the master ends the device id read sequence by nacking the last byte, thus resetting the slave device state machine and allowing the master to send the stop command. note the reading of the device id can be stopped anytime by sending a nack command. note product id bits 0 and 4 are reserved. figure 16. read device id table 1. device id device id (3 bytes) device id description 23C12 (12 bits) 11C8 (4 bits) 7C3 (5 bits) 2C0 (3 bits) manufacturer id product id density variation die rev 004221h 000000000100 0010 00100 001 s a data byte data byte 1 p by master by f-ram start address stop no acknowledge data s a rsvd slave id (f8) slave address a start address acknowledge rsvd slave id (f9) a a data byte acknowledge
CY15B256J document number: 001-90843 rev. *i page 12 of 21 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user gui delines are not tested. storage temperature ..... ............ ............... C55 ? c to +125 ? c maximum accumula ted storage time at 125 c ambient temperature ................................. 1000 h at 85 c ambient temperature ................................ 10 years ambient temperature with power applied ........... .............. .......... C55 c to +125 c supply voltage on v dd relative to v ss .........C1.0 v to +4.5 v input voltage* ......... C1.0 v to + 4.5 v and v in < v dd + 1.0 v dc voltage applied to outputs in hi-z state ........................................ C0.5 v to v dd + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ............ C2.0 v to v dd + 2.0 v package power dissipation capability (t a = 25 c) ..................................................... ............ 1.0 w surface mount lead soldering temperature (3 seconds) ................................................... ........... +260 ? c electrostatic discharge voltage human body model (jedec std jesd22-a114-b) ................ 2 kv charged device model (jedec std jesd22-c101-a) .......... 500 v latch-up current .............................................. ...... > 140 ma * exception: the v in < v dd + 1.0 v restriction does not apply to the scl and sda inputs. operating range range ambient temperature (t a ) v dd automotive-a C40 ? c to +85 ? c 2.0 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [2] max unit v dd power supply 2.0 3.3 3.6 v i dd average v dd current scl toggling between v dd C 0.2 v and v ss , other inputs v ss or v dd C 0.2 v. f scl = 100 khz C C 175 ? a f scl = 1 mhz C C 400 ? a f scl = 3.4 mhz C C 1000 ? a i sb v dd standby current scl = sda = v dd . all other inputs v ss or v dd . stop command issued. C90150 ? a i zz sleep mode current scl = sda = v dd . all other inputs v ss or v dd . stop command issued. C58 ? a i li input leakage current (except wp and a2Ca0) v ss < v in < v dd C1 C +1 ? a input leakage current (for wp and a2Ca0) v ss < v in < v dd C1 C +100 ? a i lo output leakage current v ss < v out < v dd C1 C +1 ? a v ih input high voltage (sdl, sda) 0.7 v dd Cv dd (max) + 0.3 v input high voltage (wp, a2Ca0) 0.7 v dd Cv dd + 0.3 v v il input low voltage C 0.3 C 0.3 v dd v v ol [3] output low voltage i ol = 3 ma C C 0.4 v i ol = 6 ma C C 0.6 v r in [4] input resistance (wp, a2Ca0) for v in = v il(max) 50 C C k ? for v in = v ih(min) 1CCm ? v hys [5] hysteresis of schmitt trigger inputs f scl = 100 khz, 400 khz, 1 mhz 0.05 v dd CCv f scl = 3.4 mhz 0.06 v dd CCv notes 2. typical values are at 25 c, v dd = v dd (typ). not 1 00% tested. 3. the CY15B256J does not meet the nxp i 2 c specification in the fast- mode plus (fm+ , 1 mhz) for i ol of 20 ma at a v ol of 0.4 v. 4. the input pull-down circuit is strong (50 k ? ) when the input vo ltage is below v il and weak (1 m ? ) when the input v oltage is above v ih . 5. the CY15B256J does not meet the nxp i 2 c specification in the high-speed mode (hs- mode, 3.4 mhz) for v hys of 0.1 v dd .
CY15B256J document number: 001-90843 rev. *i page 13 of 21 ac test conditions input pulse levels .................................10% and 90% of v dd input rise and fall times ..................................... ............10 ns input and output timing reference levels ................0.5 v dd output load capacitance ....................................... ..... 100 pf data retention and endurance parameter description test condition min max unit t dr data retention t a = 85 ? c10Cyears t a = 75 ? c38C t a = 65 ? c 151 C nv c endurance over opera ting temperature 10 14 C cycles capacitance parameter [6] description test conditions max unit c io input/output pin capacitance (sda) t a = 25 ? c, f = 1 mhz, v dd = v dd (typ) 8 pf c i input pin capacitance 6pf thermal resistance parameter [6] description test conditions 8-pin soic unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 146 ? c/w ? jc thermal resistance (junction to case) 48 ? c/w ac test loads and waveforms figure 17. ac test loads and waveforms 3.0 v output 100 pf 867 ? 6. these parameters are guarante ed by design and a re not tested.
CY15B256J document number: 001-90843 rev. *i page 14 of 21 ac switching characteristics over the operating range parameter [7] description fast-mode plus (fm+) [9] hs-mode [9] unit cypress parameter alt. parameter min max min max f scl [8] scl clock frequency C 1.0 C 3.4 mhz t su; sta start condition setup for repeated start 260 C 160 C ns t hd;sta start condition hold time 260 C 160 C ns t low clock low period 500 C 160 C ns t high clock high period 260 C 60 C ns t su;dat t su;data data in setup 50 C 10 C ns t hd;dat t hd;data data in hold 0 C 0 70 ns t dh data output hold (from scl at v il ) 0 C 0 C ns t r [10] t r input rise time C 120 10 80 ns t f [10] t f input fall time 20 (v dd / 5.5 v) 120 10 80 ns t su;sto stop condition setup 260 C 160 C ns t aa t vd;data scl low to sda data out valid C 450 C 130 ns t vd;ack ack output valid time C 450 C 130 ns t of [10] output fall time from v ih min to v il max 20 (v dd /5.5 v) 120 C 80 ns t buf bus free before new transmission 500 C 300 C ns t sp noise suppression time constant on scl, sda 0 50 C 5 ns figure 18. read b us timing diagram figure 19. write bus timing diagram t su:sda start t r ` t f stop start t buf t high 1/fscl t low t sp t sp acknowledge t hd:dat t su:dat t aa t dh scl sda t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda notes 7. test conditions assume signal transition time of 10 ns or les s, timing reference levels of v dd /2, input pulse levels of 0 to v dd (typ), and output loadi ng of the specified i ol and 100 pf load capa citance shown in figure 17 on page 13 . 8. the speed-related spec ifications are guar anteed characteristi c points along a continuous cur ve of operation from dc to f scl (max). 9. bus load (cb) considerat ions; cb < 550 pf for i 2 c clock frequency (scl) 1 mhz; cb < 100 pf for sc l at 3.4 mhz. 10. these parameters are guarante ed by design and are not tested .
CY15B256J document number: 001-90843 rev. *i page 15 of 21 power cycle timing over the operating range parameter description min max unit t pu power-up v dd (min) to first access (start condition) 250 C s t pd last access (stop condition) to power-down (v dd (min)) 0 C s t vr [11, 12] v dd power-up ramp rate 50 C s/v t vf [11, 12] v dd power-down ramp rate 100 C s/v t rec recovery time from sleep mode C 400 s figure 20. power cycle timing sda ~ ~ ~ ~ t pu t vr t vf v dd v dd(min) t pd v dd(min) i c start 2 i c stop 2 1rwhv 11. slope measured at any point on the v dd waveform. 12. these parameters are guarante ed by design and are not tested .
CY15B256J document number: 001-90843 rev. *i page 16 of 21 ordering information ordering code package diagram package type operating range CY15B256J-sxa 51-85066 8-pin soic automotive-a CY15B256J-sxat 51-85066 8-pin soic all these parts are pb-free. contact your local cypress sales r epresentative for avai lability of these parts. ordering code definitions option: x = blank or t blank = standard; t = tape and reel temperature range: a = automotive-a (C40 ? c to +85 ? c) x = pb-free package type: s = 8-pin soic j = i 2 c f-ram density: 256 = 256-kbit voltage: b = 2.0 v to 3.6 v f-ram cypress 15 cy b 256 j s x a x -
CY15B256J document number: 001-90843 rev. *i page 17 of 21 package diagram figure 21. 8-pin soic (150 mils) package outline, 51-85066 51-85066 *i
CY15B256J document number: 001-90843 rev. *i page 18 of 21 acronyms document conventions units of measure acronym description ack acknowledge cmos complementary metal oxide semiconductor eia electronic industries alliance i 2 c inter-integrated circuit i/o input/output jedec joint electron devices engineering council lsb least significant bit msb most significant bit nack no acknowledge rohs restriction of hazardous substances r/w read/write scl serial clock line sda serial data access soic small outline integrated circuit wp write protect symbol unit of measure c degree celsius hz hertz kb 1024 bit khz kilohertz k ? kilohm mhz megahertz m ? megaohm ? a microampere ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt
CY15B256J document number: 001-90843 rev. *i page 19 of 21 document history page document title: CY15B256J, 256-k bit (32k 8) au tomotive serial (i 2 c) f-ram document number: 001-90843 rev. ecn no. orig. of change submission date description of change ** 4266205 gvch 01/29/2014 new data sheet. *a 4390913 gvch 06/20/2014 changed sta tus from advance to prelimina ry. updated device id : updated table 1 : replaced 004201h with 004 221h in device id (3 bytes) column. updated maximum ratings : removed machine model under ele ctrostatic discharge voltage . updated dc electrical characteristics : added values in typ for i sb and i zz parameters. splitted v ih parameter to two rows namely input high voltage (sdl, sda) and input high voltage (wp, a2Ca0). changed maximum value of v ih parameter from v dd + 0.5 v to v dd (max) + 0.3 v correspo nding to sdl, sda. changed maximum value of v ih parameter from v dd + 0.5 v to v dd + 0.3 v corresponding to wp, a2Ca0. removed v ol1 , v ol2 parameters and their details. added v ol parameter and its details. added v hys parameter and its details. updated capacitance : removed c o parameter and its details. added c io parameter and its details. updated thermal resistance : replaced tbd with values. updated ac switching characteristics : added values in max column for t aa, t vd;ack, t of parameters corresponding to hs-mode. added values in min column for t buf parameter corresponding to hs-mode. removed note in hs-mode and v dd < 2.7 v, the t su:dat (min.) spec is 15 ns. and its reference in t su;dat parameter. *b 4512788 gvch 09/24/2014 updated dc electrical characteristics : added note 3 (for the difference in i ol with respect to i 2 c specification) and referred the same note in v ol parameter. *c 4571858 gvch 11/18/2014 updated dc electrical characteristics : changed minimum value of v hys parameter from 0.1 v dd to 0.05 v dd corresponding to test condition f scl = 3.4 mhz. added note 5 (for the difference in v hys with respect to i 2 c specification) and referred the same note in v hys parameter. *d 4596783 gvch 12/17/2014 updated features : added note 1 (for the difference in i ol and v hys with respect to nxp i 2 c specification) and re ferred the same note in up to 3.4-mhz fre quency. updated two-wire interface : updated description (added description for the difference in i ol and v hys with respect to nxp i 2 c specification).
CY15B256J document number: 001-90843 rev. *i page 20 of 21 *d (cont.) 4596783 gvch 12/17/2014 updated dc electrical characteristics : changed minimum value of v hys parameter from 0.05 v dd to 0.06 v dd corresponding to test condition f scl = 3.4 mhz. updated note 3 . updated note 5 (for the difference in v hys with respect to nxp i 2 c specification). updated to new template. completing sunset review. *e 4786735 gvch 06/04/2015 changed status from preliminary to final . updated package diagram : spec 51-85066 C changed revision from *f to *g. *f 4883131 zsk / psr 09/03/2015 updated functional description : added for a complete list of related documentation, click here . at the end. updated maximum ratings : removed maximum junc tion temperature. added maximum accumulated storage time. added ambient temperatu re with power applied. *g 5084285 gvch 01/13/2016 updated ordering information : updated part numbers. updated package diagram : spec 51-85066 C changed revision from *g to *h. *h 5452594 zsk 09/28/2016 updated power cycle timing : changed minimum value of t pu parameter from 1 ms to 250 s. updated to new template. *i 6083848 gvch 02/28/2018 updated package diagram : spec 51-85066 C changed re vision from *h to *i. updated to new template. document history page (continued) document title: CY15B256J, 256-k bit (32k 8) au tomotive serial (i 2 c) f-ram document number: 001-90843 rev. ecn no. orig. of change submission date description of change
document number: 001-90843 rev. *i revised february 28, 2018 pag e 21 of 21 CY15B256J cypress semiconductor corporation, 2014-2018. this document i s the property of cypress semiconductor corporation and its sub sidiaries, including spansion llc (cypress). this document, including any software or firmware included or referenced in th is document (software), is owned by cypress under the intelle ctual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and tre aties and does not, except as specifically stated in this parag raph, grant any license under its patents, copyrights, trademar ks, or other intellectual property rights. if the software is not accompani ed by a license agreement and you do not otherwise have a writt en agreement with cypress governing the use of the software, th en cypress hereby grants you a personal, non-exclusive, nontransferable li cense (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source cod e form, to modify and reproduce the software solely for use with cypress h ardware products, only internally within your organiation, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributo rs), solely for use on cypress hardware product units, and (2) under those claims of cypresss patents that are infringed by t he software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware produc ts. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the etent permitted by applicable law, cypress makes no war ranty of any kind, epress or implied, with reard to this docu ment or any software or accompanyin hardware, includi n, but not limited to, the im plied warranties of merchantability and fitness for a particula r purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informa tion or programming code, is provided only for reference purpos es. it is the responsibility of the user of this document to properly des ign, program, and test the functionality and safety of any appl ication made of this information and any resulting product. cy press products are not designed, intended, or authoried for use as critical c omponents in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support d evices or systems, other medical devices or systems (including resuscitat ion equipment and surgical implants), pollution control or haa rdous substances management, or other uses where the failure of the device or system could cause personal inury, death, or propert y damage (unintended uses). a critical component is any compo nent of a device or system whose failure to perform can be reas onably expected to cause the failure of the device or system, or to af fect its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unint ended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims fo r personal inury or death, ari sing from or related to any unint ended uses of cypress products . cypress, the cypress logo, spansion, the spansion logo, and com binations thereof, wiced, psoc, capsense, e-usb, f-ram, and tr aveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and bran ds may be claimed as property of their respective owners. sales, solutions, an d legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturers representati ves, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 mcu cypress developer community community | projects | video | blogs | training | components technical support cypress.com/support

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